1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of high performance small area SRAM cells and, even more particularly, to the manufacture of high performance small area SRAM cells having polysilicon diode loads.
2. Discussion of the Related Art
Static random access memory (SRAM) is used in computers as memory that is used by the microprocessor or central processing unit to store instructions and data from programs that are currently being used by the computer. The SRAM memory often used in this way is generally known as cache and is located between the microprocessor and the memory known as main memory. To attain the maximum benefits that SRAM can provide, the SRAM cache memory is ideally manufactured on the microprocessor chip which makes the SRAM cell area critical. Main memory is typically dynamic random access memory (DRAM). The SRAM cells used in the cache memory is optimized to run at the speed of the microprocessor. The reason that SRAM is not normally used for main memory is that because SRAM is optimized to run at the speed of the microprocessor it is more costly than DRAM and takes more chip space. This is because, in order to make the RAM run at the speed of the microprocessor it is necessary to use more transistors, typically four to six transistors per bit, to allow high-speed direct access to information in the memory by the microprocessor. DRAM memory typically uses 1 transistor per bit. This means that less memory is available per unit area on an SRAM chip and results in higher cost. Because of the increasing requirements of modern memory-hungry applications which are reaching multiple-megabyte proportions, DRAM will remain the memory of choice for main memory. However, modern computer systems require more cache memory to allow the microprocessor to fetch and process information at full speed. As the speed of the microprocessors increases and as more use of multitasking increases, the requirements for more higher speed SRAM memory will continue to grow. In addition, to achieve the full speed direct access, it is also becoming necessary for the computer designer to continue to design the cache memory to be manufactured on the main CPU chip.
For this reason, the size of the SRAM memory cell is very important. Numerous methods and devices have been conceived and tried in order to shrink the size of the individual SRAM memory cell. The comparison standard remains the classic CMOS (complementary metal on silicon) six transistor design consisting of a CMOS R-S flip-flop and two transmission gates to allow for the necessary read and write functions. The standard load devices in the R-S flip-flop in the six transistor SRAM memory cell are p-channel transistors. However, the p-channel transistors are not critical and can be replaced with passive loads such as "poly load," diode loads (reverse biased, leakage current only), and depletion NMOS loads. Plain low resistance material works, but draws too much current for practical large RAM (random access memory) arrays. Prior art poly loads and diode loads entail thin film deposition masking, doping, and some physical area in the cell.
What is needed is a smaller SRAM cell that can be manufactured using standard logic process technology. A standard logic process technology is defined as a process technoloy having N+ and P+ polysilicon gates with a refractory metal on top of the N+ and P+ lateral junctions to "short out" these lateral junctions.